The above-noted patent discloses a planar, bi-lateral switching integrated circuit comprising four vertical NPN transistors sharing a common collector, with leads between the emitters and bases of adjacent pairs. The effective circuit, shown in FIG. 1 of the accompanying drawings, is a lateral triac comprising eight transistors, the NPN's noted above and four horizontal PNP's sharing a common base, in a transistor bridge construction.
Because all junctions reach a single surface, the device can be made photosensitive. In the basic configuration it is provided with a pair of gate terminals. When a gate current is applied between one of the gate terminals and an associated main terminal, or when a light-generated photocurrent reaches a certain magnitude, the device is triggered. Because of the symmetrical construction, AC circuits may be controlled. More particularly, a single gate current can trigger the device in both quadrants I and III.
This device is called a "photrac" because it can best be described as a photosensitive triac.
The basic photrac circuit (FIG. 1) is necessarily a junction isolated device, though it will be appreciated that the whole device could be included in a dielectrically isolated circuit including other elements. In the basic circuit one transistor in each pair will block in either direction depending on its biasing. Its function in the blocking state, however, is essentially that of a diode. In its active state, of course, it functions as a transistor. A dielectrically isolated or DI photrac can be constructed employing discrete diodes replacing two of the integral transistors of the basic structure, the diodes functioning only as diodes, and this is described in the above-mentioned co-pending application, and is shown in FIG. 2. A pair of transistors Q9, Q10 are constructed in common collector configuration, with diodes D1, D2 across their respective emitter and base terminals. The main terminals are connected to the respective emitters, and the device is gated at the respective bases. A lateral PNP transistor QL is inherently part of the structure. Those skilled in the art will perceive that this device, in operation, will be similar to a pair of SCR's in the inverse-parallel or "back-to-back" mode.
A simple and effective method of constructing this device is dielectric isolation (DI). A polycrystalline silicon matrix is provided with three "tubs" of single crystal N-type silicon buried therein, each tub being entirely surrounded by a layer of silicon dioxide which insulates it from the matrix. The techniques for producing such dielectrically isolated structures are well-known in the art and need not be detailed herein. The bases of the transistors Q9, Q10, and the "P" sides of the diodes D1, D2 may be formed in a single diffusion of P-type impurities. A diffusion of N-type impurities is then carried out to form the emitter regions of the transistors. The lateral PNP transistor QL is formed inherently. Application of leads etc. is conventional.
The advantages of the basic photrac (FIG. 1), including gate triggering or light triggering and monolithic construction, are manifest. The high voltage capacities afforded by dielectric isolation, as in the FIG. 2 device, are also clear. However, in many applications these combined features are not required. More particularly, it has been perceived that from an applications point of view and for economy of production, there is need for a junction isolated device that functions as back-to-back SCR's, but one in which each gate can trigger only in a single quadrant, or, which can be light-triggered only (e.g. with floating gates). In other words, a device that functions like the DI photrac (FIG. 2) but is built like the basic photrac (FIG. 1) is useful, and that is what the present invention accomplishes.